Profile

Byungsub Kim 사진
Profile.
Name Byungsub Kim
Organization Dept of Electrical Enginrg
Telephone 279-2382
E-mail byungsub@postech.ac.kr
Homepage http://analog.postech.ac.kr/

Education

  • 2004~2010 MASSACHUSETTS INSTITUTE OF TECHNOLOGY (MIT) (박사-전자전기)
  • 2002~2004 MASSACHUSETTS INSTITUTE OF TECHNOLOGY (MIT) (석사-전자전기)
  • 1997~2000 POSTECH (학사-전자전기)

Career

  • 2010~2012 : INTEL CORPORATION
  • 2010~2011 : INTEL CORPORATION

Profession

  • 집적회로 설계
  • 고속 인터커넥트 설계
  • 설계 자동화

Journal Papers

International

  • A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 53, 144-154 (2018)
  • An On-chip Learning Neuromorphic Autoencoder with Current-Mode Transposable Memory Read and Virtual Lookup Table, IEEE Transactions on Biomedical Circuits and Systems, , 12, 161-170 (2018)
  • An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 53, 404-417 (2018)
  • A Phase-Interpolator based Fractional-Counter for All Digital Fractional-N Phase-Locked Loop, IEEE Transactions on Circuits and Systems-II, , 64, 249-253 (2017)
  • All-Synthesizable Current-Mode Transmitter Driver for USB2.0 interface, IEEE Transactions on Very Large Sale Integration SYSTEMs, , 25, - (2017)
  • A 250- μW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 64, 106-110 (2017)
  • A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and LUT for Non-Uniform ADC-Sample-Clock Generation, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, , 11, 87-97 (2017)
  • Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation, IEEE Transactions on Very Large Scale Integration Systems, , 25, 1821-1830 (2017)
  • Investigation on the Worst Read Scenario of a ReRAM Crossbar Array, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, , 25, 2402-2410 (2017)
  • An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 64, 1067-1071 (2017)
  • A Self-Biased Current-Mode Amplifier with an Application to 10-bit Pipeline ADC, IEEE Transactions on Circuits and Systems I: Regular Papers, , 64, 1706-1717 (2017)
  • A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors, IEEE Transactions on Biomedical Circuits and Systems, , 11, 523-533 (2017)
  • A Phase-Interpolator based Fractional-Counter for All Digital Fractional-N Phase-Locked Loop, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 249-253 (2017)
  • All-Synthesizable Current-Mode Transmitter Driver for USB2.0 interface, EEE Transactions on Very Large Scale Integration (VLSI), , 25, 788-792 (2017)
  • A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement, IEEE Journal of Solid-State Circuits, , 51, 1902-1914 (2016)
  • A Reconfigurable and Portable Highly Sensitive Biosensor Platform for ISFET and Enzyme-based Sensors, IEEE Sensors, , 16, 4443-4451 (2016)
  • A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 51, 1890-1901 (2016)
  • A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: Regular Papers, , , - (2016)
  • A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , , - (2016)
  • A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization, IEEE Transactions on Circuits and Systems-I: Regular Papers, , , - (2016)
  • A SNR-Enhanced Mutual-Capacitive Touch-Sensor ROIC Using an Averaging With Three Specific TX Frequencies, a Noise Memory, and a Compact Delay Compensation Circuit, IEEE Sensors, , 16, 6931-6938 (2016)
  • All-Synthesizable 5-Phase-Locked Loop for USB 2.0, Journal of Semiconductor Technology and Science, , 16, 352-358 (2016)
  • An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 62, 1335-1344 (2015)
  • A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer, IEEE Transactions on Biomedical Circuits and Systems, , 9, 138-151 (2015)
  • EMI Issues in Pseudo-Differential Signaling for SDRAM Interface, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 455-462 (2015)
  • An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 404-416 (2015)
  • An In-Band Noise Filtering 32-tap FIR-Embedded Delta Sigma Digital Fractional-N PLL, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 342-348 (2015)
  • An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 326-333 (2015)
  • Cost-Efficient and Automatic Large Volume Data Acquisition Method for On-Chip Random Process Variation Measurement, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 184-193 (2015)
  • An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 155-167 (2015)
  • Analytical Formulas for Tradeoff Among Channel Loss, Length, and Frequency of RC- and LC-Dominant Single-Ended Interconnects for Fast Equalized Link Tradeoff Estimation, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, , 5, 1497-1506 (2015)
  • An LCD-VCOM-Noise Resilient Mutual-Capacitive Touch-Sensor IC Chip With a Low-Voltage Driving Signal, IEEE SENSORS JOURNAL, , 15, 4595-4602 (2015)
  • The Oscillation Frequency of CML-based Multipath Ring Oscillators, Journal of Semiconductor Technology and Science, , 15, 671-677 (2015)
  • A Single-Stage 37 dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical Imaging, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 14, 579-587 (2014)
  • A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 987-991 (2014)
  • A 0.5-V, 1.47-mu W 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 840-844 (2014)
  • An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 49, 2618-2630 (2014)
  • An Approximate Closed-Form Channel Model for Diverse Interconnect Applications, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 61, 3034-3043 (2014)
  • Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 481-485 (2014)
  • Current-Mode Transceiver for Silicon Interposer Channel, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 49, 2044-2053 (2014)
  • Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 14, 463-470 (2014)
  • An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, , 8, 799-809 (2014)
  • A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier, IEEE Trans. on Circuits and Systems-II, , 60, 142-146 (2013)
  • A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 60, 91-95 (2013)
  • A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation, IEEE Journal of Solid-State Circuits, , 48, 2118-2127 (2013)
  • A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL, IEEE Journal of Solid-State Circuits, , 48, 2795-2804 (2013)
  • A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design, Journal of Semiconductor Technology and SCience, , 13, 482-491 (2013)
  • A 1.9-GHz Fractional-N Digital PLL With Subexponent Delta Sigma TDC and IIR-Based Noise Cancellation, IEEE Transaction on circuits and Systems II, , 59, 721-725 (2012)
  • An Energy-efficient Equalized Transceiver for RC-dominant Channels, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 45, 1186-1197 (2010)
  • A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 44, 3526-3538 (2009)
  • Characterization of Equalized and Repeated Interconnects for NoC Applications, IEEE DESIGN & TEST OF COMPUTERS, , 25, 430-439 (2008)

Domestic Journal Papers

General Journal Papers

  • An Integrated Potentiostat, IEEE Transactions on Circuits and Systems II: Express Briefs, , , - (2017)
  • 고속 System-in-Package 인터커넥트 기술 동향, IDEC Newsletter, , 192, 10-13 (2013)

Conference Proceedings

  • A 7.8Gb/s/pin 1.96pJ/b Compact Single-Ended TRX and CDR with Phase-Difference Modulation for Highly Reflective Memory Interfaces, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, - (2018)
  • A 10-GHz Multi-purpose Reconfigurable Built-in Self-Test Circuit for High-Speed Links, IEEE Asian Solid-State Circuits Conference, 0, 0, - (2017)
  • A 16.6-pJ/b 150-Mb/s Body Channel Communication Transceiver with Decision Feedback Equalization Improving > 200x Area Efficiency, IEEE SYMPOSIUM ON VLSI CIRCUITS, 0, 0, - (2017)
  • An FFE TX with 3.8x Eye Improvement by Automatic Impedance Adaptation for Universal Compatibility With Arbitrary Channel and RX Impedances, IEEE SYMPOSIUM ON VLSI CIRCUITS, 0, 0, - (2017)
  • A Coefficient-Error-Robust FFE for a Silicon Interposer Channel, ., 0, 0, - (2017)
  • A Wide Range Delay Locked Loop for DDR4, ., 0, 0, - (2017)
  • A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, - (2017)
  • A 0.0047mm2 Highly Synthesizable TDC- and DCO-Less Fractional-N PLL with a Seamless Lock Range of fREF to 1GHz, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, - (2017)
  • A 9.3nW All-in-One Bandgap Voltage and Current Reference Circuit, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, - (2017)
  • A Quadrature Relaxation Oscillator with a Process-Induced Frequency-Error Compensation Loop, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, - (2017)
  • 오디오용 쵸퍼 안정화 방식을 이용한 저잡음 증폭기, 대한전자전기공학회 추계종합학술대회, 0, 0, - (2016)
  • All Synthesizable 6Gb/s Voltage-Mode Transmitter for Serial Link, IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 0, 0, - (2016)
  • An ECG Monitoring System Using Android Smart Phone, IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-ASIA (ICCE-ASIA), 0, 0, - (2016)
  • All Synthesizable Transmitter Driver and Data Recovery Circuit for USB 2.0 Interface, IEEE INTERNATIONAL SOC DESIGN CONFERENCE, 0, 0, - (2016)
  • A Low-Power LDO Circuit With A Fast Load Regulation, IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 0, 0, - (2016)
  • 시리얼 링크를 위한 디지털 합성화 된 다중 위상고정루프, ., 0, 0, - (2016)
  • Full-speed USB PHY_LINK 소자와 델타-모듈레이터 ADC를 이용한 안드로이드 스마트폰용 오실로스코프, ., 0, 0, - (2016)
  • A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using A Three-Level Balanced Coding Scheme, IEEE SYMPOSIA ON VLSI TECHNOLOGY AND CIRCUITS, 0, 0, - (2016)
  • All Synthesizable Current-Mode Transmitter Driver for Serial Link Interface, 18TH INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION AND COMMUNICATION (ICEIC), 0, 0, - (2016)
  • All-Synthesizable 5-Phase Phase-Locked Loop, 18TH INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION AND COMMUNICATION (ICEIC), 0, 0, - (2016)
  • A Threshold Voltage Variation Calibration Algorithm for An ISFET-Based Low-Cost pH Sensor System, IEEE SENSORS, 0, 0, - (2015)
  • An Approximate Condition to Avoid Reverse Leakage Current in ReRAM Crossbar Design, IEEE INTERNATIONAL SOC DESIGN CONFERENCE, 0, 0, - (2015)
  • A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design, IEEE/ACM INTERNATIONAL COMPUTER-AIDED DESIGN CONFERENCE, 0, 0, - (2015)
  • A reduced-size look-up-table for ADC sample-times of a single-chip non-uniform-sampling digital-beamformer for ultrasound medical imaging, IEEE INTERNATIONAL SOC DESIGN CONFERENCE, 0, 0, - (2015)
  • A Mutual-Capacitive Touch Sensor ROIC Using a PLL to Reduce LCD Noise by Synchronizing ROIC TX Clock to LCD Clock, IEEE SENSORS, 0, 0, - (2015)
  • An FPGA-Based Embedded System for Portable and Cost-Efficient Bio-sensing: A Low-Cost Controller for Biomedical Diagnosis, IEEE INTERNATIONAL CIRCUITS AND SYSTEMS SYMPOSIUM, 0, 0, - (2015)
  • An Input Pole Tuned Switching Equalization Scheme for High-Speed Serial Links, IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 0, 0, - (2015)
  • A 35dB-Linear Variable Gain Amplifier Circuit of Digital-Beamformer for Ultrasound Medical Imaging, 30TH INTERNATIONAL TECHNICAL CONFERENCE ON CIRCUITS SYSTEMS, COMPUTERS AND COMMUNICATIONS (ITC-CSCC), 0, 0, - (2015)
  • High-speed USB 2.0 device 용 Link 및 Data Acquisition System, ., 0, 0, - (2015)
  • Comprehensive Methodology for ReRAM and Selector Design Guideline of Cross-Point Array, IEEE INTERNATIONAL MEMORY WORKSHOP, 0, 0, - (2015)
  • A 29-nW bandgap reference circuit, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, - (2015)
  • EMI issues in pseudo-differential signaling for SDRAM interface, ., 0, 0, - (2015)
  • A Voltage-Scalable 10-b Pipelined ADC with Current- Mode Amplifier, PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 0, 0, - (2014)
  • A 0.4 V Driving Multi-Touch Capacitive Sensor with the Driving Signal Frequency set to (n+0.5) Times the Inverse of the LCD VCOM Noise Period, IEEE 2014 ISCAS, 0, 0, - (2014)
  • An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, 426-427 (2014)
  • A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface, INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, - (2014)
  • A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, 50-51 (2014)
  • Full-speed USB 2.0 device용 Link및 Application Layer 칩, 대한전자전기공학회 추계종합학술대회, 0, 0, - (2013)
  • All-digital USB 2.0 device Full-speed PHY 칩, 대한전자공학회 하계학술대회, 0, 0, - (2013)
  • RC-dominant 채널의 간단한 전달함수 모델을 이용한 RC-dominant 인터커넥트 길이와 손실의 Trade-off 분석, 대한전자공학회, 0, 0, - (2013)
  • Micro-second 레벨의 지연시간을 가지는 Voltage Controlled Delay Line, 2012년도 대한전자공학회 하계학술대회 제 35권 1호, 0, 0, - (2012)
  • An analytical model of scaled RC-dominant wires for high-speed wireline transceiver design, PROCEEDINGS OF INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 0, 0, - (2011)
  • Designing Energy-efficient Low-Diameter On-chip Networks with Equalized Interconnects, PROCEEDINGS OF HIGH PERFORMANCE INTERCONNECTS, 0, 0, - (2009)
  • A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion, IEEE INTERNATINOAL SYMPOSIUM ON VLSI CIRCUITS DIGEST OF TECHNICAL PAPERS, 0, 0, - (2009)
  • A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, - (2009)
  • A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS Technology, IEEE INTERNAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, - (2009)
  • Equalized Interconnect for On-chip Network: Modeling and Optimization Framework, PROCEEDINGS OF IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, 0, 0, - (2007)
  • Power-Adaptive Operational Amplifier with Positive Feedback Self-Biasing, PROCEEDINGS OF IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 0, 0, - (2006)

Invited Talk or Presentations

  • An FFE TX with 3.8x Eye Improvement by Automatic Impedance Adaptation for Universal Compatibility with Arbitrary Channel and RX Impedances, Symp. on VLSI Cir. (VLSIC), 0, 0, - (2017)
  • A 16.6-pJ/b 150-Mb/s Body Channel Communication Transceiver with Decision Feedback Equalization Improving 200% Area Efficiency, Symposium on VLSI Circuits (VLSIC), 0, 0, - (2017)
  • A Coefficient-Error-Robust FFE TX with 230% Eye Variation Improvement Without Calibration in 65-nm CMOS Technology, IEEE CAS SOCIETY KOREAN WORKSHOP ON CIRCUITS AND SYSTEMS, 0, 0, - (2017)
  • A 0.0047mm2 Highly Synthesizable TDC and DCO-less Fractional-NPLL with a Seamless Lock - Range off RER to 1GHz, IEEE International Solid-State Circuits Conference (ISSCC), 0, 0, - (2017)
  • A Quadrature Relaxation Oscillator with a Process-Induced Frequency-Error Compensation Loop, IEEE International Solid-State Circuits Conference (ISSCC), 0, 0, - (2017)
  • A 9.3nW All-in-One Bandgap Voltage and Current Reference Circuit, IEEE International Solid-State Circuits Conference (ISSCC), 0, 0, - (2017)
  • A Time-Based Receiver with 2-tap DFE for a 12Gb/s/pin Single-EndedTransceiver of Mobile DRAM Interface in 0.8V 65nm CMOS, IEEE International Solid-State Circuits Conference (ISSCC), 0, 0, 400-402 (2017)
  • Read Margin Analysis in an ReRAM Crossbar Array, ., 0, 0, - (2016)
  • Hierarchical Design Automation for Electronics, EDA SUMMER WORKSHOP, 0, 0, - (2015)
  • An Energy-Efficient Equalized Transceiver for RC-dominant Channels, POSTECH-NTU SILICON INTERPOSER WORKSHOP, 0, 0, - (2015)
  • DFE-IIR Equalization, POSTECH-NTU SILICON INTERPOSER WORKSHOP, 0, 0, - (2015)
  • A Coefficient-Error-Robust FFE TX with 230% Eye-Variation Improvement Without Calibration in 65nm CMOS Technology, CMOS EMERGING TECHNOLOGY RESEARCH, 0, 0, - (2014)
  • 수신 단 TIA 터미네이션 기법의 단일 신호선 듀오바이너리 송수신 단 회로, ., 0, 0, - (2014)
  • LCD VCOM Noise 주파수 (n+0.5) 배의 주파수를 인가 신호 주파수로 이용하는 다중 정전용량 터치 센서, ., 0, 0, - (2014)
  • 오픈루프 시간차이 증폭기를 이용한 고해상도 Time-to-Digital Converter, ., 0, 0, - (2014)
  • USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling, ., 0, 0, - (2014)
  • CMOS 이미지 센서 인터페이스용 Gb/s SerDes, ., 0, 0, - (2014)
  • An Experimental Verification of A Scaled RC-dominant Interconnect Line Model of High-speed Wireline, ., 0, 0, - (2014)
  • A Single-Stage 40dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Analog Front End, ., 0, 0, - (2014)
  • A Winner-Take-All Neuromorphic IC in 65nm CMOS, ., 0, 0, - (2014)
  • Verilog Synthesis of USB 2.0 Full-speed Device PHY IP, ., 0, 0, - (2013)
  • A Power Reduction of 37% in a Differential Serial Link Transceiver by Increasing the Termination Resistance, ., 0, 0, - (2013)
  • Revisiting High-Speed Interconnect Channel Modeling, ., 0, 0, - (2013)
  • Design Automation Techniques for High-Speed Interconnects, ., 0, 0, - (2013)
  • High slew-rate 1.2V Class-AB OTA, ., 0, 0, - (2013)
  • A Neuromorphic IC with Spike-Timing-Dependent-Plasticity, ., 0, 0, - (2013)
  • A Winner-Take-All Neuromorphic IC in 65nm CMOS, ., 0, 0, - (2013)
  • A Neuromorphic IC with Spike-Timing-Dependent-Plasticity, ., 0, 0, - (2013)
  • A spread Spectrum Clock Generator Using Phase/Frequency Boosting with a Peak Power Reduction 14.6dB, RMS Jitter 1.45ps and Power 4.8mW/GHz for USB 3.0, ., 0, 0, - (2012)
  • 실리콘 인터포저 인터커넥트 연구동향, ., 0, 0, - (2012)
  • NCO용 Pulse Width Modulator 회로, ., 0, 0, - (2012)
  • Future State-of-the-Art Electrical Interconnect, ., 0, 0, - (2010)
  • Energy Efficient Wireline Communication Over RC-dominant Channels, ., 0, 0, - (2009)

Books

Research Activities

  • 생체-화학-전기 검출기 개발을 위한 다 학제간 교류 및 공동 연구 기획, 포항공과대학교 (2012-2013)
  • A ROBUST INTERCONNECT WITH LOW SENSITIVITY TO NANO-SCALE DEVICE'S UNCERTAINTY, 포항공과대학교 (2012-2013)
  • COMPREHENSIVE RESEARCH ON THE NEXT GENERATION LOW POWER ULTRA-HIGH SPEED INTERCONNECT CIRCUIT AND CROSS-LAYER DESIGN, 재단법인한국연구재단 (2012-2013)
  • 학부생연구프로그램-김도윤(전자)-계수에러에 강력한 트랜스미트 피드 포워드 이궐라이제이션 분석, 포항공과대학교 (2012-2012)
  • ., 삼성전자(주) (2012-2013)
  • A ROBUST INTERCONNECT WITH LOW SENSITIVITY TO NANO-SCALE DEVICE'S UNCERTAINTY, 포항공과대학교 (2013-2014)
  • 신규부임교수 기자재지원비(학과부담), 포항공과대학교 (2013-2014)
  • 학생인건비통합관리과제, 포항공대산학협력단 (2013-2020)
  • 4.8350_1차년도 이월과제, 재단법인한국연구재단 (2013-2014)
  • COMPREHENSIVE RESEARCH ON THE NEXT GENERATION LOW POWER ULTRA-HIGH SPEED INTERCONNECT CIRCUIT AND CROSS-LAYER DESIGN, 재단법인한국연구재단 (2013-2014)
  • ., 한국과학기술연구원 (2013-2013)
  • 콘택트렌즈형 지속/자가구동 헬스 모니터링 플랫폼 기술 개발, 한국과학기술연구원 (2014-2014)
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  • DEVELOPMENT OF A LOW-POWER BIOSENSOR DRIVING CIRCUIT, 한국과학기술연구원 (2015-2016)
  • 코딩기법을 이용한 저항성 CROSS-POINT ARRAY 메모리의 성능 개선 연구, 에스케이하이닉스 주식회사 (2015-2016)
  • POSTECH-NTU SILICON INTERPOSER INTERCONNECT COOPERATIVE RESEARCH AND EXCHANGE PROGRAM, 재단법인한국연구재단 (2015-2016)
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  • DEVELOPMENT OF A LOW-POWER BIOSENSOR DRIVING CIRCUIT, 한국과학기술연구원 (2016-2017)
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  • COMPREHENSIVE RESEARCH ON THE NEXT GENERATION LOW POWER ULTRA-HIGH SPEED INTERCONNECT CIRCUIT AND CROSS-LAYER DESIGN, 재단법인한국연구재단 (2017-2018)
  • DEVELOPMENT OF A LOW-POWER BIOSENSOR DRIVING CIRCUIT, 한국과학기술연구원 (2017-2018)
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  • A MULTIPURPOSE NANO-BIOSENSOR SYSTEM IN A SILICON INTERPOSER PACKAGE, 재단법인한국연구재단 (2018-2019)
  • 실시간 고해상도 IN-VIVO IMAGING을 위한 초고속 체내데이터 전송기술 연구실, 재단법인한국연구재단 (2018-2019)
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  • A MULTIPURPOSE NANO-BIOSENSOR SYSTEM IN A SILICON INTERPOSER PACKAGE, 재단법인한국연구재단 (2019-2020)
  • FUNDAMENTAL RESEARCH LABORATORY OF ULTRA-HIGH SPEED DATA TRANSMISSION FOR REAL-TIME HIGH-RESOLUTION IN-VIVO IMAGING, 재단법인한국연구재단 (2019-2020)

IP

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  • 김병섭,최민수, 완화된 임피던스 매칭을 제공하는 송신 장치 및 수신 장치, 한국, 10-2018-0062901 (2018)
  • 김병섭,이수은, 고반사 인터커넥트를 위한 위상차 변조 송수신기 및 클럭 복구회로, 한국, 10-2018-0057992 (2018)
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