Professor Sung Je Hong
High Performance Computer Lab.
Department of Computer Science and Engineering POSTECH

San 31, Hyoja-Dong, Pohang, KOREA, 790-784
Tel : +82-562-279-2250
Email : sjhong@postech.ac.kr
학력 및 주요경력
전문분야
전문학술지논문
학술회의논문
연구실적
저서 및 기타 학술활동
강의과목


  • 1983-University of Illinois at Urbana-Champaign(공학박사-전자계산학)
  • 1979-Iowa State University(공학석사-전자계산학)
  • 1973-서울대학교(공학사-전자공학)
  • 주요경력
    •
  • 199603-199808 : 포항공과대학교, 전자계산학과 주임교수
  • 198906-현재 : 포항공과대학교 전자계산학과, 교수
  • 198306-198906 : General Electric Company, Staff
  • 197909-198305 :Univ. of Illinois Urbana-Champagn, 연구조교
  • 197709-197905:Iowa State Univ., 연구조교
  • 197601-197707:동양전산(주), 엔지니어
  • 197305-197512:중앙경리단, 프로그래머

  • Parallel Processing
  • Fault-Tolerance
  • VLSI Testing
  • Computer-Aided Design of VLSI, VLSI Architectures

J. H. Park, S. J. Hong, J. Kim, S. Lee, "MUMEC: Protocol for Multicasting with Membership Control," IEE Electronics Letters, Vol 39, No. 2, pp 257-259, Jan 2003.
H. Lee, J. Kim, S. J. Hong, and S. Lee, "Processor Allocation and Task Scheduling of Matrix Chain Products on Parallel Systems," IEEE Transactions on Parallel and Distributed Systems, Vol. 14, No. 3., 2003. (SCIE 0.851)
H. Lee, J. Kim, S. J. Hong, and S. Lee, "Task Scheduling Using a Block Dependency DAG for Block-oriented Sparse Cholesky Factorization," Parallel Computing, Vol. 29, pp. 135-159, 2003. (SCIE 0.572)
H. Nam, J. Kim, S. J. Hong, and S. Lee, "Probabilistic Checkpointing," IEICE Transactions on Information and Systems, Vol. E85-D, No. 7, pp. 1093-1104, July 2002. (SCIE 0.144)
H-S Heo, S. J. Hong, J-K Seong, M-S Kim, and G. Elber "The Intersection of Two Ringed Surfaces and Some Related Problems," Graphical Models, Vol. 63, No. 4, pp. 228-244, July 2001. (SCI 0.821)
H. W. Kim, S. Lee, J. Kim, and S. J. Hong, "A Kernel-level Software Network Interface for Distributed Shared Memory System," Journal of Electrical Engineering and Information Science, Vol. 5(1), pp. 1-7, Jan. 2000.
J-H Lee, S. J. Hong, and M-S Kim, "Polygonal Boundary Approximation for a 2D General Sweep Based on Envelope and Boolean Operations", The Visual Computer, Vol. 16, pp. 208-240, Spriger-Verlag, 2000
W. Y. Lee, S. J. Hong, and J. Kim, "On the Configuration of Switch-Based Networks with Wormhole Routing", Journal of Interconnection Networks, Vol. 1, No. 2, pp. 95-114, World Scientific Publishing Company, 2000
H. Lee, J. Kim, S. J. Hong, "Evaluation of Two Load-Balancing Primary-Backup Process Allocation Scemes", IEICE Transactions on Information and Systems, E82-D, 1535-1544, IEICE, 199912
S. H. Chae, J. Kim, S. J. Hong, and S. Lee, "Design and Analysis of the Dual-Torus Network", New Generation Computing, Vol. 17, pp. 229-254, Springer-Verlag, 199905
O-H Kwon, S. J. Hong, J. Kim, "A Booloean Factorization Using an Extended Boolean Matrix", IEICE Trans. on Information and Systems, Vol. E81-D, No. 12, pp. 1466-1472, IEICE, 199812
W. Y. Lee, S. J. Hong, and J. Kim, "Dynamic Load Distribution on Meshes with Broadcasting", Int. Journal of High Speed Computing, Vol. 9, No. 4, pp. 337-357, World Scientific Publishing Company, 199812
장태익, 이주행, 김명수, 홍성제, "B-스플라인 동작을 이용한 Generalized Cylinder의 직접제어", 컴퓨터 그래픽스 학회논문지, 제4권 제2호, pp. 47-55, 한국컴퓨터그래픽스학회, 199812
김정범, 권오형, 홍성제, "ASIC용 메모리 컴파일러 설계", 전자공학회논문지, 제35권, pp. 23-32, 대한전자공학회, 199808
J. B. Kim, S. J. Hong, and J. Kim, "A CMOS Built-In Current Sensing Circuit", Int. Journal of Electronics, Vol. 85, No. 2, pp. 181-205, IEEE, 1998
J. B. Kim, S. J. Hong, and J. Kim, "Design of a Built-In Current Sensor for IDDQ Testing", Journal of Solid-State Circuits, Vol. 33, N0. 8, 1266-1272, IEEE, 1998
T-I Chang, J-H Lee, M-S Kim, and S. J. Hong, "Direct Manipulation of Generalized Cylinders based on B-spline Motion", The Visual Computer, 14, 228-239, Springer-Verlag, 1998
김정범, 홍성제, 김종, "IDDQ 테스팅을 위한 내장형 전류 감지 회로 설계", 전자공학회논문지, 제34권 C편 제8호, pp. 49-63, 대한전자공학회, 199708
이완연, 김동승, 홍성제, 김종, "메쉬형 컴퓨터를 위한 계층적 동적 부하균등화 기법", 정보과학회 논문지(A), 제24권 제3호, 311-320, 한국정보과학회, 199703
J. B. Kim, S. J. Hong, and J. Kim, "New Circuits for XOR and XNOR Functions", Int. J. Electronincs, 82, 131-143, 199702
M-H Kyung, M-S Kim, and S. J. Hong, "A New Approach to Through-the-Lens Camera Control", Graphical Models and Image Processing, 58, No. 3, 262-285, Academic Press, Inc., 199605
홍성제, "CMOS 회로에 있어서의 합선 및 절선결함 테스팅", 전자공학회지, pp. 124-130, 대한전자공학회, 199512
경민호, 김명수, 홍성제, "효율적인 Through-the Lens 카메라 제어 기법", 컴퓨터그래픽스학회논문, pp. 99-108, 컴퓨터그래픽스학회, 199503
홍성제, "VLSI 테스팅의 문제점과 연구현황", 씨에이디 연구회지, 제1권 제1호, pp. 28-30, 씨에이디 연구회, 199201
S. J. Hong and S. Muroga, "Absolute Minimization of Completely Specified Switching Functions", IEEE Trans. Computer,, Vol. C-40, pp. 53-65, IEEE, 199101
S. J. Hong, "The Design of a Testable Parallel Multiplier", IEEE Trans. Computers, Vol. C-39, pp.411-416, IEEE, 199003
S. J. Hong, "Existence Algorithms for Synchronizing/Distinguishing Sequences", IEEE Trans. Computers, Vol. C-31, pp.234-237, IEEE, 198103


G. J. Lee, S. J. Hong, and J. Kim, "A Multiple Gateway Mobile IP Hierarchy Supporting Load Sharing and Fault-Tolerance," IASTED International Conference on Communications and Computer Networks, pp.480-485 IASTED/ Cambridge, MA, USA, Nov. 2002.
H.-C. Nam, J. Kim, S. J. Hong, and S. Lee , "A Secure Checkpointing System," 2001 Pacific Rim International Symposium on Dependable Computing (PRDC 2001), pp.49--60 IEEE Computer / Seoul, Korea, Dec. 17, 2001.
W. Y. Lee, S. J. Hong, J. Kim, and SW. Lee, "A Dynamic Load Balancing Algorithm on Switch-Based Networks", Proc. of the ISCA 13th International Conference on Parallel and Distributed Computing Systems, 302-307, Las Vegas, USA, 20000808
S. J. Hong, "A Universal Routing", Int. Workshop on Fault-Tolerant Control and Computing, FTCC-1, 117-124, Seoul, Korea, 20000522
H. Lee, J. Kim, S. J. Hong, ans S. Lee, "Task Scheduling using a Block Dependency DAG for Block-Oriented Sparse Cholesky Gactorization", Proceedings of the 2000 ACM Symposium on Applied Computing, Vol. 2, pp. 641-648, Como, Italy, 20000319
H-C Nam, J. Kim, S. J. Hong, and S. Lee, "Reliable Probabilistic Checkpointing", PRDC 1999, Hong Kong, 19991216
Y. H. Lee, J. Kim, and S. J. Hong, "A New Multicast Tree Rearrangement Algorithm," IASTED International Conference on Parallel and Distributed Computer and Networks, pp.142-145, Brisbane, Australia, Dec. 1998.
B. Kim, J. Kim, S. J. Hong, S. Lee, "A Real-Time Communication Method for Wormhole Switching Networks," 1998 International Conference on Parallel Processing (ICPP-27), pp. 527--534, Minneapolis, U.S.A. Aug. 1998
T. Chang, J-H Lee, M-S Kim and S. J. Hong, "Direct Manipulation of Generalized Cylinders," Geometric Modeling and Processing '98, pp. 151-160, Pohang, Korea, April 7-8, 1998.
K. Ahn, J. Kim, and S. J. Hong, "Fault-Tolerant Real-Time Scheduling Using Passive Replicas", PRFTS '97, Taiwan, 199712
W. Lee, S. J. Hong, and J. Kim, "Dynamic Load Distribution on a Mesh with a Single Bus", ICPDA '97, Seoul, Korea, 199712
H. Lee, J. Kim, and S. J. Hong, "Evaluation of Matrix Chain Products on Parallel Systems", The 9th ICPAD, Washington DC, USA, 199710
O-H Kwon, J. Kim, and S. J. Hong, "Real-Time Job Scheduling in Hypercube Systems2", ICPP '97, Bloomingdale, IL, USA, 199708
H. C. Nam, J. Kim and S. J. Hong, "Probablistic Checkpointing", FTCS-27, Seattle, WA, USA, 199706
H. Lee, J. Kim, and S. J. Hong, "Processor Allocation for Matrix Products", The 6th Parallel Computing Workshop, Kawasaki, Japan, 19961112
S. J. Hong, "Test Generation for Asynchronous Circuits Using the 15-V Logic", SEMICON-KOREA '96, Seoul, Korea, 199601
S. Chae, J. Kim, and S. J. Hong, "DTN: A New Partitionable Torus Topology", ICPP '95, Oconomowoc, WI, USA, 199508
S. J. Hong, H. J. Choi, and J. Kim, "Multi-Level Logic Synthesis Based on the Modified Map-Factoring Method", JTC-CSCC '95, Kumamoto, Japan, 199507
H. Lee, J. Kim, and S. J. Hong, "Fault-Tolerant Process Allocation with Load Balancing", PRFTS '95, Newport Beach, CA, USA, 1995
M-H Kyung, M-S Kim, and S. J. Hong, "Through-the lens Camera Control with a Simple Jacobian Matrixs", Proc. of Graphics Interface '95, 171-178, 1995
S. J. Hong, "A 15－Valued Fast Test Generation for Combinational Circuits”, The 2nd Asian Test Symposium, Beijing, China, pp.113－118, Nov. 1993.
S. J. Hong, H. T. Ju, and Y. Choi, "Test Generation by Goal Transformation", ICVC, Seoul, Korea, 199110
S. J. Hong, "Algebraic Method for the Minimization of Switching Functions", ICVC, Seoul, Korea, 198910
S. J. Hong, "An Easily Testable Parallel Multiplier," Proc. 18th Annual Symp. on Fault-Tolerant Computing(FTCS-18), Tokyo, Japan, 1988.
S. J. Hong, "A DFT Technique for an Unsigned Multiplier," 11th Annual IEEE Workshop on Design for testability, Vail, Colorado, Apr. 1988.
S. J. Hong, "Computer Aided Design of VLSI," Autumn Workshop '86, Seoul, Korea, Oct. 1986.
S. J. Hong, "A CMOS PLA Compiler," GOSAM Meeting, Syracuse, NY, 1985.
S. J. Hong, "A Structured Approach to Test Vector Generation," Proc. IEEE Int. Conf. on Computer Design, pp. 757-762, 1984.


"3D painting기반 형성 solid texture모델링 및 형성처리기술 개발" 한국과학재단, 19990701-20000630
"테스팅을 고려한 대용량 메모리 설계" 현대전자산업(주), 19970701-20010630
"과학계산용 병렬알고리즘 개발" KISTEP, 19961201-19990809
"기가비트망에서의 부하균등화 연구" 한국과학재단, 19960901-19990831
"자기검진 및 결함포용 기능을 갖는 대용량 메모리 설계기술연구" 한국전자통신연구원(ETRI), 19960101-19971031
"Chip Planner 개발" 현대전자, 19951201-19961130
"교환기 소프트웨어 고장인성에 관한 연구" 한국전자통신연구원(ETRI), 19950501-19951231
"HLS 및 BTI 명령수행 칩 설계" 신기술연구조합, 19950501-19960630
"8-bit MCU용 C 컴파일러 개발" 현대반도체, 19950301-19960229
"ASIC용 ROM/RAM Compiler의 개발" 19940701-19950630
"장애 종류에 따른 Redundancy 설계 방안 연구" 한국전자통신연구원(ETRI), 19930901-19940831
"Redundancy S/W 설계방안 연구" 한국전자통신연구원(ETRI), 19930901-19940430
"VLSI 회로를 위한 테스트 자동생성에 관한 연구" 한국과학재단, 19920301-19940228
"주문형 반도체 설계시스템 개발 및 초고주파 필터 설계제작" 19920101-19941231
"일반 스윕 경계선의 생성에 관한 연구" 포항공과대학교, 19900401-20000331


강성호, 김규철, 소병세, 홍성제, "메모리 테스트", 대영사, 567p, (2001.03).
강성호, 박은세, 장훈, 최호용, 홍성제, "테스팅 및 테스팅을 고려한 설계", 홍릉출판사, 398, 19980320, 서울특별시 강북구 수유5동 455-60,


  • 기타 학술 활동
    •
S. J. Hong, "Design of a Minimal Programmable Logic Arrays", Univ. of Illinois at Urbana-Champaign, 1983
S. J. Hong, "Existence Algorithms for Synchronous/Distingusing Sequences", Iowa State University, 1979


  • 특허
    •
홍성제,김종,김정범, "회로검사용 전류 감지 회로", 한국, 출원번호 1997-000890,


  • cse604 병렬처리
  • cse601 결함포용
  • ece341 오토마타 및 형식언어
  • ece702 컴퓨터 시스템 특론

Copyright (C) 2001 POSTECH HPC Lab., All Rights Reserved
Last updated, February 24, 2001