교원프로필

백록현 사진
교원에 대한 정보를 나타내는 표입니다.
성명 백록현
소속 전자전기공학과
전화번호 054-279-2220
E-mail rock8201@postech.ac.kr
Homepage https://sites.google.com/view/team-postech-ac-kr/home

학력

  • 2006.03 ~ 2011.02 포항공과대학교 (박사-반도체소자/회로)
  • 2004.03 ~ 2006.02 포항공과대학교 (석사-반도체소자/회로)
  • 2000.03 ~ 2004.02 고려대학교 (학사-전기전자전파)

주요경력

  • 2015.08 ~ 2017.01 : 삼성전자반도체연구소 LOGIC TD팀
  • 2011.04 ~ 2015.06 : SEMATECH

전문분야

  • FinFET, Gate-All-Around Nanowire, NanoSheet FET, III-V MOSFET
  • 3D TCAD and RC simulation
  • CMOS Device Physics and Modeling: compact model, virtual-source model
  • Reliability, noise, parasitic RC analysis
  • Technology node benchmark and tech definition, Power/Performance/Area analysis

학술지

국제전문학술지

  • Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs, IEEE Access, , 9, 16728-16735 (2021)
  • Origin of Incremental Step Pulse Programming (ISPP) slope degradation in charge trap nitride based multi-layer 3D NAND flash, Solid-State Electronics, , 175, - (2021)
  • Observation of mobility and velocity behaviors in ultra-scaled L-G=15 nm silicon nanowire field-effect transistors with different channel diameters, SOLID-STATE ELECTRONICS, , 164, - (2020)
  • Threshold Voltage Variations Induced by Si1-xGex and Si1-xCx of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors, JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, , 20, 4684-4689 (2020)
  • Sensitivity of Source/Drain Critical Dimension Variations for Sub-5-nm Node Fin and Nanosheet FETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 67, 258-262 (2020)
  • Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application, IEEE ACCESS, , 8, 35873-35881 (2020)
  • Improved Long-Term Responses of Au-Decorated Si Nanowire FET Sensor for NH3 Detection, IEEE SENSORS JOURNAL, , 20, 2270-2277 (2020)
  • Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 67, 2732-2737 (2020)
  • Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing, IEEE ACCESS, , 8, 159351-159370 (2020)
  • Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, , 8, 1272-1280 (2020)
  • Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications, IEEE ACCESS, , 8, 189395-189403 (2020)
  • A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications, IEEE ACCESS, , 8, 196975-196978 (2020)
  • Metal Source-/Drain-Induced Performance Boosting of Sub-7-nm Node Nanosheet FETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 66, 1868-1873 (2019)
  • Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications, JAPANESE JOURNAL OF APPLIED PHYSICS, , 58, - (2019)
  • Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain, IEEE ACCESS, , 7, 38593-38596 (2019)
  • Bottom oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node, IEEE ACCESS, , 7, 75762-75767 (2019)
  • Electron trapping and extraction kinetics on carrier diffusion in metal halide perovskite thin films, Journal of Materials Chemistry A, , 7, 25838-25844 (2019)
  • Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node, IEEE ACCESS, , 7, 172290-172295 (2019)
  • Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory, JAPANESE JOURNAL OF APPLIED PHYSICS, , 57, - (2018)
  • Systematic analysis of oxide trap distribution of 4H-SiC DMOSFETs using TSCIS and its correlation with BTI and SILC behavior, SOLID-STATE ELECTRONICS, , 140, 18-22 (2018)
  • Analog Figure-of-Merits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between Inversion-Mode and Junctionless Nanowire FETs, JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, , 18, 6598-6601 (2018)
  • Study on Random Dopant Fluctuation in Core-Shell Tunneling Field-Effect Transistors, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 65, 3131-3135 (2018)
  • Multi-V-th Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing, IEEE Journal of the Electron Devices Society, , 6, 861-865 (2018)
  • Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, , 57, - (2018)
  • Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs, IEEE Journal of the Electron Devices Society, , 6, 942-947 (2018)
  • Work function consideration in vacuum field emission transistor design, JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, , 35, - (2017)
  • High-Performance Logic Transistor DC Benchmarking Toward 7 nm Technology-Node Between III-V and Si Tri-gate n-MOSFETs Using Virtual-Source Injection Velocity Model, SOLID-STATE ELECTRONICS, , 116, 100-103 (2016)
  • Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 63, 3399-3405 (2016)
  • Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node, IEEE ELECTRON DEVICE LETTERS, , 36, 994-996 (2015)
  • Investigation of RC Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 62, 3441-3444 (2015)
  • Impact of Spacer Dielectric Constant on Parasitic RC and Design Guidelines to Optimize DC/AC Performance in 10 nm Node Si-Nanowire FETs, JAPANESE JOURNAL OF APPLIED PHYSICS, , 54, 4DN08-1-4DN08-5 (2015)
  • Physical DC and Thermal Noise Models of 18 nm Double-Gate Junctionless pMOSFETs for Low Noise RF Applications, JAPANESE JOURNAL OF APPLIED PHYSICS, , 54, 4DC08-1-4DC08-6 (2015)
  • Investigation of Process-Induced Performance Variability and Optimization of the 10 nm Technology Node Si Bulk FinFETs, SOLID-STATE ELECTRONICS, , 96, 27-33 (2014)
  • STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity, IEEE ELECTRON DEVICE LETTERS, , 34, 1082-1084 (2013)
  • Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications, IEEE ELECTRON DEVICE LETTERS, , 33, 1234-1236 (2012)
  • Electrical characteristics of 20-nm junctionless Si nanowire transistors, SOLID-STATE ELECTRONICS, , 73, 7-10 (2012)
  • Characterization and Modeling of 1/f Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides, IEEE TRANSACTIONS ON NANOTECHNOLOGY, , 10, 417-423 (2011)
  • C-V Characteristics in Undoped Gate-All-Around Nanowire FET Array, IEEE ELECTRON DEVICE LETTERS, , 32, 116-118 (2011)
  • Comparison of Series Resistance and Mobility Degradation Extracted from n-and p-Type Si-Nanowire Field Effect Transistors Using the Y-Function Technique, JAPANESE JOURNAL OF APPLIED PHYSICS, , 49, 4DN06-01-4DN06-05 (2010)
  • Characteristics of the Series Resistance Extracted from Si Nanowire FETs Using the Y-Function Technique, IEEE TRANSACTIONS ON NANOTECHNOLOGY, , 9, 212-217 (2010)
  • A new physical 1/f noise model for double stack high-k gate dielectric MOSFETs, IEEE ELECTRON DEVICE LETTERS, , 30, 1365-1367 (2009)
  • Low-Frequency Noise After Channel Soft Oxide Breakdown in HfLaSiO Gate Dielectric, IEEE ELECTRON DEVICE LETTERS, , 30, 523-525 (2009)
  • A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 Gate Stack nMOSFETs, MICROELECTRONIC ENGINEERING, , 88, 3411-3414 (2009)
  • Low-temperature performance of nanoscale MOSFET for deep-space RF applications, IEEE ELECTRON DEVICE LETTERS, , 29, 775-777 (2008)

국내전문학술지

일반학술지

학술회의논문

  • SRAM Performance Variations Induced by Source/Drain Mole Fraction Change of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors, The 18th International Nanotech Symposium & Exhibition, 0, 0, - (2020)
  • Neural Network Based 14-nm Node Fully-Depleted FET Design for AC Applications of SoC and 3DIC, The 18th International Nanotech Symposium & Exhibition, 0, 0, - (2020)
  • TSV-to-Transistor Noise Coupling Characterizations for Sub 5-nm Node Fin- and Nanosheet FETs in 3D-IC, The 18th International Nanotech Symposium & Exhibition, 0, 0, - (2020)
  • Interface trap curing effects on high-k gate stack (Al/Al2O3/Si-sub) by rapid thermal anneal (RTA), The 18th International Nanotech Symposium & Exhibition, 0, 0, - (2020)
  • Electrical and Dielectric Properties of TiO2 Based MIS Capacitor, The 18th International Nanotech Symposium & Exhibition, 0, 0, - (2020)
  • Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications, 4th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020, 0, 0, - (2020)
  • Power, Performance and Area Analysis of Source/Drain Patterning n/p FinFETs based 6T-SRAM cell for 3-nm technology node, 제 27회 반도체학술대회, 0, 0, - (2020)
  • Defect Curing Effects on High-k Gate Stack (Al/Al2O3/Si-sub) by Using H2 Plasma Treatment and Rapid Thermal Anneal, 제 27회 반도체학술대회, 0, 0, - (2020)
  • Demonstration of TiO2 based ultra high-k (k=30) MIS capacitor and its electrical properties, 제 27회 반도체학술대회, 0, 0, - (2020)
  • The Origin of Incremental Step Pulse Programming (ISPP) Slope Degradation in NAND Flash Memory, 제 27회 반도체학술대회, 0, 0, - (2020)
  • Extensive Analysis of Incremental Step Programming Pulse (ISPP) Slope Degradation in NAND Flash Memory, the 17th International Nanotech Symposium & Exhibition, 0, 0, - (2019)
  • Comparison of virtual source velocity and apparent mobility in shrunk Lg=15 nm n/p-SNWFETs with various channel diameters, the 17th International Nanotech Symposium & Exhibition, 0, 0, - (2019)
  • Impact of Thermo-Mechanical Stress Induced by Through-Silicon Vias on Performance Variations of 5-nm Node Si-Nanosheet FETs, the 17th International Nanotech Symposium & Exhibition, 0, 0, - (2019)
  • Scalability of OTS Integrated PCM for 3-D Stackable Cross-point Array Structure Using TCAD Simulation, the 17th International Nanotech Symposium & Exhibition, 0, 0, - (2019)
  • Critical dimension variations of sub 5-nm node fin and nanosheet FETs, the 17th International Nanotech Symposium & Exhibition, 0, 0, - (2019)
  • The Effects of Realistic U-shaped Source/Drain on DC/AC Performances of Silicon Nanosheet FETs for Sub 5-nm Node SoC Applications, 2019 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 0, 0, 133-135 (2019)
  • Observation of Mobility and Velocity Behaviors in Ultra Scaled Lg=15 nm Silicon Nanowire pMOSFETs with Different Channel Diameters, 제26회 한국반도체학술대회, 0, 0, - (2019)
  • Vth Variation Induced by S/D Mole Fraction and Si/SiGe Intermixing of Si-NSFETs, 제26회 한국반도체학술대회, 0, 0, - (2019)
  • Design Strategy of 20nm node single PRAM cell based on TCAD Simulation, 제1회 반도체공학회 학술대회, 0, 0, - (2018)
  • Geometric Optimization of Silicon Gate-All-Around Field-Effect Transistors (GAAFETs) for DC/AC Performances, 제1회 반도체공학회 학술대회, 0, 0, - (2018)
  • Observation of Mobility and Velocity as Channel Diameter Change in the Shrunk Lg = 18nm Silicon Nanowire MOSFETs, 제1회 반도체공학회 학술대회, 0, 0, - (2018)
  • Nanosheet Number and Width Optimization of Multi Stacked NanoSheet FET for 7-nm Node SoC Application, Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials, 0, 0, 877-878 (2018)
  • Vth variation of string SONOS NAND Flash depending on single grain boundary and stored electron charges in an adjacent cell, Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials, 0, 0, 793-794 (2017)
  • Improving DMMP (Salin simulant) Sensing Characteristics of TFQ Functionalized Graphene Chemiresistive Sensors, Proceedings of the 17th IEEE international Conference on Nanotechnology, 0, 0, 675-677 (2017)
  • High-Performance III-V Devices for Future Logic Applications, ELECTRON DEVICES MEETING (IEDM), 2014 IEEE INTERNATIONAL, 0, 0, - (2014)
  • Impact of High-k Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2014)
  • Physical DC and Thermal Noise Models of 18 nm DG Junctionless pMOSFETs, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2014)
  • Electrostatics and Performance Benchmarking using all Types of III-V Multi-Gate FinFETs for sub 7nm Technology Node Logic Application, INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY DIGEST, 0, 0, - (2014)
  • Sub-100 nm InGaAs Quantum-Well (QW) MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for Low-Power Logic Applications, ELECTRON DEVICES MEETING (IEDM), 2013 IEEE INTERNATIONAL, 0, 0, - (2013)
  • Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node, ELECTRON DEVICES MEETING (IEDM), 2013 IEEE INTERNATIONAL, 0, 0, - (2013)
  • VLSI Processed InGaAs on Si MOSFETs with Thermally Stable, Self-Aligned Ni-InGaAs Contacts Achieving: Enhanced Drive Current and Pathway Towards a Unified S/D Contact Module, ELECTRON DEVICES MEETING (IEDM), 2013 IEEE INTERNATIONAL, 0, 0, - (2013)
  • Extraction of Series Resistance on Junctionless and Inversion-mode nanowire FET through the Method based on Y-function, INTERNATIONAL CONFERENCE ON DEVICE RESEARCH CONFERENCE, 0, 0, - (2013)
  • Effects of Layout and Process Parameters on Device/Circuit Performance and Variability for 10nm Node FinFET Technology, INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY DIGEST, 0, 0, - (2013)
  • Effects of fin height of tapered FinFETs on the sub-22nm System on Chip (SoC) application using TCAD simulation, INTERNATIONAL SYMPOSIUM ON VLSI-TSA, 0, 0, - (2013)
  • Comprehensive Study of Process-Induced Device Performance Variability and its Optimization for 14 nm Technology Node Bulk FinFETs, INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 0, 0, - (2012)
  • Modeling and Analysis of the Parasitic Series Resistance in Raised Source/Drain FinFETs with Polygonal Shaped Epitaxy, INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 0, 0, - (2012)
  • Conformal, low-damage shallow junction technology (Xj~5nm) with optimized contacts for FinFETs as a Solution Beyond 14nm Node, INTERNATIONAL WORKSHOP ON JUNCTION TECHNOLOGY, 0, 0, - (2012)
  • Comparative Study of Geometry-dependent Capacitances of Planar FETs and Double-Gate FinFETs: Optimization and Process Variation, INTERNATIONAL SYMPOSIUM ON VLSI-TSA, 0, 0, - (2012)
  • Reliable Extraction of Series Resistance in Silicon Nanowire FETs Using Y-function Technique, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2011)
  • Analysis of Bottom Channel Effect in Silicon Nanowire FET based on Bulk-Silicon: Reduction of Parasitic Capacitance caused by SiGe layer, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2011)
  • Analysis of Parasitic Bottom Capacitance in n- and p-type Si-Nanowire Field Effect Transistors on Bulk, IEEE-NANO, 0, 0, - (2011)
  • Investigation of GIDL Behavior in Si-Nanowire FET with Hot Carrier Stress, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS(한국반도체학술대회), 0, 0, - (2011)
  • Characteristics and Modeling of Si-nanowire FETs (Invited paper), IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY, 0, 0, - (2010)
  • Comparative Study of C-V Characteristics in Si-NWFET and MOSFET (Invited paper), IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2010)
  • C-V Characteristics and Analysis of Undoped Gate-All-Around Nanowire FET Array, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, 1277-1278 (2010)
  • Low-Frequency Noise Behavior of La-Doped Hf-Based Dielectric nMOSFETs, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2010)
  • Low‐Frequency Noise Analysis in HfO2HfO2/SiON Gate Stack nMOSFETs with Different Interfacial Layer Thickness, INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, 0, 0, - (2010)
  • GIDL analysis of underlap double gate MOSFET with variable channel thickness and doping using quantum simulation, PROCEEDINGS OF SEMICONDUCTOR SOCIETY, IEEK SUMMER CONFERENCE, 0, 0, - (2010)
  • Comparative study on device performance of Junctionless double-gate MOSFET, PROCEEDINGS OF SEMICONDUCTOR SOCIETY, IEEK SUMMER CONFERENCE, 0, 0, - (2010)
  • Characteristics of Gate-All-Around Si-NWFET, including Rsd, Cylindrical Coordinate Based 1/f Noise and Hot Carrier Effects, IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 0, 0, - (2010)
  • Accurate Extraction of Volume Trap Density from Si-Nanowire FET using the Newly Developed Cylindrical Coordinate Based 1/f noise model, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS(한국반도체학술대회), 0, 0, - (2010)
  • Impact of Dipole-induced Dielectric Relaxation on High-frequency Performance in La-incorporated HfSiON/Metal Gate nMOSFET, ELECTRON DEVICES MEETING (IEDM), 2009 IEEE INTERNATIONAL, 0, 0, - (2009)
  • Fabrication, DC and Low Frequency Noise Characteristics of Silicon Nanowire FET, PROCEEDINGS OF SEMICONDUCTOR SOCIETY, IEEK FALL CONFERENCE, 0, 0, - (2009)
  • Hot Electron Degradation Effects in 35nm InAlAs/InGaAs Metamorphic HEMT, PROCEEDINGS OF SEMICONDUCTOR SOCIETY, IEEK FALL CONFERENCE, 0, 0, - (2009)
  • Series Resistance Behavior Extracted from Silicon Nanowire Transistors Using the Y-function Technique, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, 1108-1109 (2009)
  • RF performance degradation in 100-nm metal gate/high-k dielectric nMOSFET by hot carrier effects, SOLID STATE DEVICE RESEARCH CONFERENCE, 2009. ESSDERC '09. PROCEEDINGS OF THE EUROPEAN, 0, 0, - (2009)
  • RF degradation of short channel metal gate/high-k dielectric nMOSFET by hot carrier effect, PROCEEDINGS OF SEMICONDUCTOR SOCIETY, IEEK SUMMER CONFERENCE, 0, 0, - (2009)
  • Effects of High Pressure Hydrogen Anneal Process on Performance and Reliability in HfO2/SiO2 Dielectric with Contact Etch Stop Layer Stressor, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2009)
  • High Pressure Hydrogen Annealing Effect of CESL Nitride Stressor MOSFETs with Metal Gate/High-k Dielectric on the Performance and Reliability, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2009)
  • Reliability of HfO2/SiO2 Dielectric with Strain Engineering using CESL Stressor, IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 0, 0, - (2009)
  • RF and Hot Carrier Effects in metal gate/high-k Dielectric nMOSFETs at cryogenic temperature, IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 0, 0, - (2009)
  • Effective Mobility Extraction of the Advanced MOSFETs Using RF Modeling, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS(한국반도체학술대회), 0, 0, - (2009)
  • DC and Reliability Characteristics of 45nm Node MOSFETs with using HfSiON/TiN Gate Stacks, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS(한국반도체학술대회), 0, 0, - (2009)
  • RF characteristics in Metal Gate/High-K Dielectric nMOSFETs at cryogenic temperature, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS(한국반도체학술대회), 0, 0, - (2009)
  • Effective Carrier Mobility Extraction Based on RF Modeling for Highly Leaky MOSFET Devices with Short Channel Length and Small Area, SPANISH CONFERENCE ON ELECTRON DEVICES, 0, 0, - (2009)
  • Novel Extrinsic Series Resistance Extraction Methodology for Nanoscale MOSFETs, IEEE INTERNATIONAL RF AND MICROWAVE CONFERENCE, 0, 0, - (2008)
  • A Novel Series-resistance Extraction Method for Nano-scaled nMOSFETs Considering Mobility Degradation due to Vbs, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
  • Reliability of HfO2/SiO2 Dielectric with Strain Engineering using CESL Stressor, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
  • The Performance of HfSiON/TiN Gate Stack MOSFETs for 45 nm Node LSTP Application Using Conventional Fabrication Process, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
  • Gate-Induced Drain Leakage (GIDL) Performance of Strain Engineering using CESL Stressor with High-k gate dielectric, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
  • Effective Mobility Extraction Methodology Using RF Modeling Scheme for Leaky MOSFET with Short Channel Length and Small Area, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
  • Temperature dependent performances of nMOSFET with HfLaSiO gate dielectric, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
  • Comparison of PECVD and RTCVD CESL Nitride Stressor in Reliability and Performance Improvement for High-k/Metal Gate CMOSFETs, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2008)
  • I-V modeling for nanoscale n-MOSFET from liquid-nitrogen temperature to room temperature, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2006)
  • 70nm CMOS BSIM4 Macro modeling for RFIC design, PROCEEDINGS OF SEMICONDUCTOR SOCIETY, IEEK SUMMER CONFERENCE, 0, 0, - (2006)
  • Optimized scalable I-V Modeling for 70nm Gate length Nano-CMOS using BSIM4, PROCEEDINGS OF SEMICONDUCTOR SOCIETY, IEEK SUMMER CONFERENCE, 0, 0, - (2005)

학회발표

  • An Analysis on Electrical Characteristics of Submicron-LTPS Thin-Film-Transistors, 한국반도체디스플레이기술학회, 0, 0, - (2018)
  • Effect of Elliptical Channel Shape on Memory Characteristics of Vertical 3D NAND Flash Memory, 한국반도체디스플레이기술학회, 0, 0, - (2018)
  • Low Frequency Noise in SiC Double-Implant MOSFETs, 제25회 한국반도체학술대회, 0, 0, - (2018)
  • Improved Thermal Stability and Lower Sheet Resistance of NiSi with Carbon Pre-silicidation Implant, 제25회 한국반도체학술대회, 0, 0, - (2018)
  • New multi frequency capacitance extraction methodology for leaky MOS capacitor with High-K dielectric and metal gate, INTERNATIONAL SYMPOSIUM ON ADVANCED GATE STACK TECHNOLOGY, 0, 0, - (2008)
  • Cryogenic RF Characteristics of HfO2-Gated nMOSFET, INTERNATIONAL SYMPOSIUM ON ADVANCED GATE STACK TECHNOLOGY, 0, 0, - (2008)
  • PBTI and HCI stress-induces trap generation in SiO2/HfO2 gate stack NMOSFETs and its impact on low frequency noise, INTERNATIONAL SYMPOSIUM ON ADVANCED GATE STACK TECHNOLOGY, 0, 0, - (2008)
  • RF characteristics for 70 nm MOSFETs below 77K, ASIA-PACIFIC WORKSHOP ON FUNDAMENTALS AND APPLICATIONS OF ADVANCED SEMICONDUCTOR DEVICES, 0, 0, - (2007)

단행본

  • DC Performance Variations of SOI FinFETs with Different Silicide Thickness, VIDE LEAF, 19, 백록현 (2020)
  • Gate-All-Around FETs: Nanowire and Nanosheet Structure, intechopen, 15, BAEK, RH (2020)
  • Nanoelectronic Device Applications Handbook, CRC Press, 940, BAEK, RH (2017)
  • Nanowire Field Effect Transistors: Principles and Applications, Springer New York, 26, 김대만 (2014)

연구실적

  • 백록현_신규부임교수 기자재지원(1차_학과), 포항공과대학교 (2017-2018)
  • 백록현_신규부임교수 연구비지원(1차_학과), 포항공과대학교 (2017-2018)
  • 백록현_신규부임교수 기자재지원(1차_대학), 포항공과대학교 (2017-2018)
  • (민간)5 NM급 이하 차세대 LOGIC 소자 원천요소기술 개발, (사)한국반도체연구조합 (2017-2017)
  • (정부)5 NM 급 이하 차세대 LOGIC 소자 원천요소기술개발, 산업자원부 (2017-2017)
  • SUB 7NM NODE 향 MULTI-GATE MOSFET 소자 설계, 재단법인한국연구재단 (2017-2018)
  • (정부)5NM 노드 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, 산업자원부 (2017-2018)
  • (민간)5NM 노드 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, (사)한국반도체연구조합 (2017-2018)
  • 학생인건비통합관리과제, 포항공대산학협력단 (2018-2022)
  • 백록현_신규부임교수 기자재지원(대학_2차), 포항공과대학교 (2018-2019)
  • 백록현_신규부임교수 연구비지원(2차_학과), 포항공과대학교 (2018-2019)
  • SUB 7NM NODE 향 MULTI-GATE MOSFET 소자 설계, 재단법인한국연구재단 (2018-2019)
  • 3D NAND FLASH의 APC(ABNORMAL PROGRAM CELL) 원인 인자 규명, 에스케이하이닉스 주식회사 (2018-2020)
  • (정부)5NM 노드 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, 산업자원부 (2018-2018)
  • 4.14714 이월과제, 재단법인한국연구재단 (2018-2019)
  • (민간)5NM 노드 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, (사)한국반도체연구조합 (2018-2018)
  • SUB 7NM NODE 향 MULTI-GATE MOSFET 소자 설계, 재단법인한국연구재단 (2019-2020)
  • 백록현_신규부임교수 기자재지원(3차_대학), 포항공과대학교 (2019-2020)
  • 백록현_신규부임교수 연구비지원(3차_학과), 포항공과대학교 (2019-2020)
  • SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, 한국산업기술평가관리원 (2019-2019)
  • (민간)SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, (사)한국반도체연구조합 (2019-2019)
  • 스마트 콘텍트렌즈 플랫폼 기술 개발, 주식회사 인터로조 (2019-2019)
  • 4.15043_이월과제, 주식회사 인터로조 (2019-2019)
  • 4.16222_이월과제, 주식회사 인터로조 (2019-2019)
  • 연구개발과제[2015년 신설], 포항공과대학교 (2019-2030)
  • AI 기법을 이용한 DRAM PERI. 소자의 공정 및 성능 최적화, 에스케이하이닉스 주식회사 (2020-2021)
  • SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화 , 한국산업기술평가관리원 (2020-2020)
  • (민간)SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 재안 및 성능 최적화, (사)한국반도체연구조합 (2020-2020)
  • 3D NAND FLASH의 APC(ABNORMAL PROGRAM CELL)의 원인 인자 규명 , 에스케이하이닉스 주식회사 (2020-2021)
  • 3D-NAND FLASH의 초고난도 산업 난제 해결을 위한 융합형 메모리 AI 플랫폼 개발, 재단법인한국연구재단 (2020-2021)
  • 기초연구실 부서운영비, 포항공대산학협력단 (2020-2021)
  • 신소자 및 CMOS 동시 집적을 위한 8인치 공정 플랫폼 개발, 재단법인한국연구재단 (2020-2020)
  • 신소자 및 CMOS동시 집적을 위한 8인치 공정 플랫폼 개발, 재단법인한국연구재단 (2021-2021)
  • SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, 한국산업기술평가관리원 (2021-2021)
  • 4.0020639_이월과제, 재단법인한국연구재단 (2021-2021)
  • (민간)SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 재안 및 성능 최적화, (사)한국반도체연구조합 (2021-2021)
  • 3D-NAND FLASH의 초고난도 산업 난제 해결을 위한 융합형 메모리 AI 플랫폼 개발, 재단법인한국연구재단 (2021-2022)

IP

  • 백록현,윤준식,최현철,윤혁, 반도체 제조 파라미터 설정 방법 및 이를 수행하기 위한 컴퓨팅 장치, 한국, 10-2020-0133780 (2020)
  • 백록현,윤준식, 단일 구조의 캐스코드 소자 및 이의 제조방법, 한국, 10-2020-0116933 (2020)
  • 백록현,윤준식,정진수,이승환, 소스/드레인 에피 크기를 조절할 수 있는 전계효과 트랜지스터 및 이의 제조방법, USA, 16/898,706 (2020)
  • 백록현,윤준식,정진수,이승환, 펀치스루 스토퍼가 필요 없는 전계효과 트랜지스터 및 이의 제조방법, USA, 16/750,292 (2020)
  • 백록현,윤준식,이승환,정진수, 금속 소스/드레인 기반 전계효과 트랜지스터 및 이의 제조방법, USA, 16/562,693 (2019)
  • 백록현,윤준식,정진수,이승환, 에피텍셜 구조를 갖는 소스/드레인 영역이 축소된 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2019-0074877 (2019)
  • 백록현,윤준식,정진수,이승환, 에피텍셜 구조를 갖는 소스/드레인 영역이 축소된 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2019-0074877 (2019)
  • 백록현,윤준식,정진수,이승환, 펀치스루 스토퍼가 필요 없는 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2019-0011571 (2018)
  • 백록현,윤준식,정진수,이승환, 펀치스루 스토퍼가 필요 없는 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2019-0011571 (2018)
  • 백록현,윤준식,이승환,정진수, 금속 소스/드레인 기반 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2018-0114050 (2018)